1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a p-channel transistor having a barrier implant in the source-side of the channel to control migration of subsequently introduced, high diffusivity implant species therein.
2. Description of the Related Art
Associated with fabrication of PMOSFETs are several difficulties not found in NMOSFET fabrication. Among these is the problem of redistribution of implanted boron used to form source/drain areas in a PMOSFET. Dopants with relatively heavy ionic masses, such as arsenic, are implanted to form source/drain implant areas in NMOSFETs. These heavy ions have relatively small projected implant ranges and little channeling when implanted. Further, arsenic has a low diffusivity, such that minimal redistribution occurs as a result of post-implant annealing.
In contrast, boron has a relatively low atomic mass. As a result, junctions formed using boron are deeper than junctions formed with heavier n-type impurities. Due to its lower mass, boron has a longer implant range, even at lower implant energies. Ion channeling by boron also increases the depth of the implant. In addition, boron has a high diffusivity. Post-implant anneal can cause significant redistribution of boron, leading to both a deeper junction due to vertical redistribution and a narrowed channel due to lateral redistribution. The presence of boron adjacent to and even within the channel adds capacitance and resistance to the source/drain pathway. This added resistance, generally known as parasitic resistance, can have many deleterious effects. For example, parasitic resistance can decrease the saturation drive current and the overall speed of the transistor. Thus, in order to maximize drive current, it is desirable to maintain separation between the source impurity distribution and the channel.
While it would seem beneficial to decrease the drain-side parasitic resistance as well as the source-side parasitic resistance, the drain-side parasitic resistance is nonetheless needed to minimize the problem of hot carrier injection ("HCI") as the lateral dimensions of PMOSFETs decrease to the submicron range. HCI is a phenomenon whereby the kinetic energy of the charge carriers (holes or electrons) is increased as the carriers are accelerated through large potential gradients and subsequently become trapped within the gate dielectric. The greatest potential gradient, often referred to as the maximum electric field ("E.sub.m "), occurs near the drain during saturated operation of a transistor. More specifically, the electric field is predominant at the lateral junction of the drain adjacent the channel. As hot carriers travel to the drain, they lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs which migrate to and become injected within the gate dielectric near the drain junction. Vacancy and interstitial positions within the gate dielectric generally become electron traps, resulting in a net negative charge density within the gate dielectric. Unfortunately, the trapped charge may accumulate over time, causing the transistor threshold voltage to undesirably shift from its design specification.
To overcome the problems related to HCI, an alternative drain structure known as the lightly doped drain ("LDD") has grown in popularity. The LDD structure advantageously absorbs some of the potential into the drain and thus reduces E.sub.m. A conventional LDD structure is one in which a light concentration of dopant is self-aligned to the gate conductor followed by a heavier concentration of dopant self-aligned to the gate conductor on which two sidewall spacers have been formed. The purpose of the first implant dose is to produce a lightly doped section (i.e., an LDD area) at the gate edge immediately adjacent the channel. The second implant dose forms a heavily doped source/drain region spaced from the channel a distance dictated by the thickness of the sidewall spacer. A dopant gradient (i.e., graded junction) therefore results at the interface between the LDD area and the channel as well as between the LDD area and the source/drain region. Lightly doped drain areas are typically formed simultaneously on both the source and drain sides to facilitate processing. Because the addition of an LDD implant adjacent the channel adds capacitance and resistance to the source/drain pathway, however, transistor fabrication often involves a compromise between maximizing drive current and minimizing hot carrier injection.
Further, as the dimensions of transistor features have become increasingly smaller to provide for faster and more complex integrated circuit devices, the shrinkage of device dimensions has given rise to various problems. Microelectronic manufacturers have primarily focused on reducing the lateral dimensions of transistor devices to achieve the desired operational speed of an integrated circuit. After implantation of dopants into the source/drain regions and subsequent diffusion of the dopants, the actual distance between the source/drain regions becomes less than the physical channel length and is often referred to as the effective channel length ("L.sub.eff "). In VLSI designs, as the physical channel length becomes small, so too must L.sub.eff. Decreasing L.sub.eff of a transistor generally leads to so-called short-channel effects ("SCE") in which the transistor's properties, e.g., the transistor threshold voltage, undesirably vary from their design specification. Absent a comparable reduction in the depth of the source/drain regions, the severity of the SCE resulting from a decrease in L.sub.eff may be profound. Accordingly, it has become necessary to scale down the vertical dimensions of the source/drain regions, (i.e., the depth of the implant), to ensure proper operation of transistor devices.
The formation of shallow source/drain regions (i.e., junctions) is, however, rather difficult for PMOSFET devices which include boron-implanted junctions. Due to the relatively high diffasivity and channeling of boron atoms, implanted boron can penetrate deeply into the substrate. While using very low implant energies of boron might produce relatively shallow junctions, advances in technology are required to make available low-energy ion implanters before such low implant energies can be realized. Reducing the junction depth has residual value in decreasing lateral diffusion as well. Thus, a low energy implant can provides some protection against SCE. However, a shallow implant, or an implant with low dosage, can increase the parasitic resistance of the source/drain junctions. Moreover, forming contacts to relatively shallow junctions has several drawbacks. A contact layer which consumes the underlying source/drain junctions is often used during contact formation. For example, a refractory metal may be deposited across the source/drain junctions and heated to initiate a reaction between the metal and the underlying silicon, thereby forming a low resistivity self-aligned silicide ("salicide") upon the junctions. Unwanted junction spiking may also occur if aluminum contacts abut the relatively shallow junctions. Consequently, the junctions may exhibit large current leakage or become electrically shorted. Therefore, precautions must be taken to prevent excessive consumption of the shallow junctions (i.e., junction spiking) during contact formation.
Attempts have been made to overcome the problems associated with junction depth reduction. One approach involves using selective silicon growth ("SSG") with rapid thermal anneal ("RTA") processing, as described in "High Performance Half-Micron PMOSFETs With 0.1 .mu.m Shallow P.sup.+ N Junction Utilizing Selective Silicon Growth And Rapid Thermal Annealing", H. Shibata et al., IEDM Tech. Dig., 1987, pp. 590-593 (incorporated by reference as if fully set forth herein). The SSG technique is used to raise the source/drain regions above the base of an adjacent gate conductor by growing silicon selectively upon the source/drain regions. After the SSG process, RTA of the source/drain regions is performed to minimize impurity redistribution and to reduce the source/drain resistance as well as the contact resistance. However, the SSG technique, which uses selective epitaxial growth, is generally difficult to control and requires equipment typically not used by integrated circuit manufacturers. Both of these factors contribute to the high overall cost of using the SSG technique.
Another approach used to prevent the shortcomings of shallow junctions is described in "High Performance Submicron SOI/CMOS With An Elevated Source/drain Structure", J. M. Hwang et al., IEEE International SOI Conference Proceedings, 1993, pp. 132-133 (incorporated by reference as if fully set forth herein). This approach employs thinning of the channel. The extent of thinning may unfortunately fluctuate across the channel region, depending upon the physical channel length. Accordingly, it may be difficult to achieve the depth of the resulting recessed region required to reduce the source/drain resistance of the ensuing source/drain regions which are to be raised above the base of the ensuing gate conductor. A gate conductor which is not self-aligned to the recessed region of the substrate may be undesirably patterned above the substrate. As a result, a portion of the gate conductor may extend below the uppermost surface of the substrate into the recess region, while another portion of the gate conductor may terminate above the substrate surface beyond the recess region. A transistor formed in this manner may exhibit characteristics dissimilar from those designed for the transistor.
A process similar to the one above is described in "Recessed Channel (RC) SOI NMOSFETs With Self-Aligned Polysilicon Gate Formed on the RC Region", J. H. Lee et al., IEEE International SOI Conference Proceedings, 1996, pp. 122-123 (incorporated by reference as if fully set forth herein). Lee et al. generally describe a masking layer which exposes only the channel region of a substrate. During local oxidation of the channel region, oxide growth may occur underneath the edges of the masking layer in addition to upon the channel region, a phenomena known as the "bird's beak" effect. Due to the bird's beak effect, the resulting sidewall surfaces of the gate conductor may be nonvertical. As a result, the physical channel length might not be clearly defined. Further, the relatively low slope of the gate conductor sidewall surfaces may severely limit, if not eliminate, the possibility of forming dielectric sidewall spacers upon the sidewall surfaces. Therefore, the ability to form well-defined LDD areas adjacent to the gate conductor may be sacrificed by the formation of the gate conductor above a recessed region of the substrate.
It would therefore be of benefit to develop a transistor fabrication method which permits forming a transistor having maximal drive current and minimal hot carrier injection. Further, it would be beneficial to develop a method for forming a transistor with relatively shallow source/drain junctions. A transistor fabricated according to such a process would exhibit improved performance (e.g., speed). In addition, such a transistor would be less likely to experience short channel effects even if the transistor possesses a relatively short physical channel length. The transistor would also be more likely to operate according to design.